In general, there has been a tendency to increase the diameter of a wafer in current semiconductor fabrication processes so as to accomplish high integration of a ULSI (ultralarge scale integrated circuit). Also, current semiconductor fabrication has been subjected to more strict standards including the minimum width requirement of 0.13 μm or less. Further, a step of forming a multiple interconnection or multilayer interconnection structure on a wafer is essentially required for improving the quality of a semiconductor device.
Therefore, a damascene process for forming a metal wiring line has been used. In the damascene process, a wiring line is formed by the steps of: forming grooves in a dielectric on a process wafer; embedding a wiring material, such as tungsten, aluminum or copper, etc., into the grooves; and removing a surplus amount of the wiring material.
One of method for removing a surplus amount of the wiring material is CMP (chemical mechanical polishing). During the process of CMP, a wafer surface is pressed against a polishing pad that rotates relative to the surface, and chemically reactive slurry is introduced into the polishing pad during the polishing process. Such a CMP technique accomplishes planarization of a wafer surface by way of chemical and physical actions.
However, in the above described polishing technique, there is a problem in that the wafer surface is polished unevenly (ex. dishing and erosion of a wiring line are occurred.), thereby reducing the reliability of a circuit. In order to solve such a problem, there has been provided a method of protecting a wiring line by using an appropriate corrosion inhibitor, but this method has a problem in that the polishing rate is significantly reduced.